Leakage Power Estimation in SRAMs

In this paper we propose analytical models for estimating the leakage power in CMOS based SRAM designs. We identify the transistors that contribute to the leakage power in each SRAM sub-circuit as a function of the operation (read/write/idle) on the SRAM and develop parameterized leakage power models in terms of the high level design parameters and transistor widths. The models take number of rows, number of columns, read column multiplexer size and write column multiplexer size of the SRAM along with the technology parameters as input to estimate the leakage power. The developed models are validated by comparing their estimates against the power measured using SPICE simulations on industrial SRAM designs belonging to the e5001 processor core. The comparison shows that the models are highly accurate with an error margin of less than 23.9%. ∗This work was done in collaboration with Motorola corporation e500 is the Motorola processor core that is compliant with the PowerPC Book E architecture